With scaling of technology, the reduction of power and leakage current to extend battery life by utilizing specialized design techniques has become more desirable. One such specialized technique is to reduce the frequency of a clock signal and/or to adjust the supply voltage to reduce power consumption of digital circuitry while maintaining adequate performance of the device.
In digital circuits, power consumption typically varies linearly with the frequency of operation. Various methods of stopping system clocks, or lowering the operating frequency of system clocks, have been used. One such technique to reduce the operating frequency of a system clock is to change the multiplication/divide ratio of a phase locked-loop. By changing the multiplication ratio of a phase locked-loop, the output frequency of the phase locked-loop is varied. However, changing the multiplication ratio of a phase locked-loop is not a very robust technique, in that the phase locked-loop may as a result lose lock, which can go undetected, whereby a system failure would occur. Alternatively, even when the loss of a lock is detected, it takes time for a new phase locked-loop frequency, based upon a new multiplication ratio, to settle in, which may result in unpredictable system operation.
Therefore, a method of overcoming these problems would be desirable.
The present disclosure relates generally to frequency generating devices, and more specifically to a frequency generating device and method using a phase locked-loop.